Node Level Overview

The Gen9 GPU architecture is an example of a recent Intel GPU architecture that is scaled to allow for integration with the CPU. This architecture consists of a modular hierarchal design consisting of cores or Execution Units (EU) that are grouped together into SubSlices (SS) and further into Slices. The scalable nature of this device allows for configurations that can vary based on the product range being targeted.

The EUs contain Floating Point Units (FPU) with a flexible SIMD width. Similar to other GPU architectures in the market, they are optimized for high throughput computation. To mitigate this, each EU consists of a group of threads that can exploit concurrency to hide the latency of long operations. These devices typically consist of a shared data cache (L1) among the EUs in a SubSlice and an L3 for the entire device. Finally, a global thread dispatcher load balances and distributes instructions from the device level command streamer to the various SubSlices.